Add wolfBoot FIT support for loading bitstream

[dgarske]

Features

• Load and program an FPGA bitstream from an fpga sub-image in a signed FIT, using the standard U-Boot convention: sub-image type = "fpga", configuration fpga = "<node>" reference, and a compatible string selecting the load method (partial in the string selects partial reconfiguration, otherwise full). Programmed before the kernel/DTB load so PL-dependent clocks/peripherals come up first.
• New hal_fpga_load() HAL abstraction with a weak default (returns not-implemented) and per-target implementations.
  • ZynqMP (TARGET=zynq): full bitstream via the PMU firmware PM_FPGA_LOAD EEMI call (xilfpga / CSU DMA / PCAP).
  • Zynq-7000 (TARGET=zynq7000): full bitstream via a new DevC/PCAP DMA driver (UG585 ch.6) with bounded poll-loop timeouts.
  • Versal (TARGET=versal): documented not-implemented stub (PL config is a PLM Load-PDI IPI).
• fit_load_fpga() stages the bitstream to a configurable DDR address (WOLFBOOT_LOAD_FPGA_ADDRESS), decompressing gzip bitstreams (the typical mkimage output, which has no load property) bounded by WOLFBOOT_FIT_MAX_FPGA and validated by the gzip CRC32 + ISIZE.
• Generic per-board FIT configuration selection: FIT_CONFIG_SELECT=1 plus a weak hal_fit_config_name() hook lets an integrator boot a non-default configuration (e.g. conf-<board>); the default returns NULL (use the FIT default). No board-detection (GPIO/CHIPID) logic is shipped upstream.
• New build flags: FPGA_BITSTREAM, FPGA_NONFATAL (failed PL load warns and continues instead of panicking), WOLFBOOT_LOAD_FPGA_ADDRESS, FIT_CONFIG_SELECT. All opt-in; default builds are unchanged.
• fit_find_images() extended to discover the fpga node (config fpga property and type == "fpga" fallback); new fit_get_compatible() helper.
• New unit-fit-fpga unit test covering fpga discovery and compatible parsing; docs and .its template updated.

Fixes

• ZynqMP PM_FPGA_LOAD size is passed in bytes (not 32-bit words), matching stock Xilinx U-Boot and the PMU firmware xilfpga, which divides by the word length internally.
• Decompress gzip fpga sub-images that have no load property to the staging address, instead of failing closed.
• Place the weak hal_fpga_load() / hal_fit_config_name() defaults in hal/hal.c (linked into every target) rather than a region of libwolfboot.c that is compiled out for the Xilinx targets, fixing an undefined-reference link error.

Testing

Results testing FIT image boot with FPGA image on ZCU102:

Load address 0x10000000
Attempting boot from P:A
Boot partition: 0x80337F0 (sz 87561128, ver 0x1, type 0x401)
Loading image from disk...
done (3675 ms)
Boot partition: 0x80337F0 (sz 87561128, ver 0x1, type 0x401)
Checking image integrity...
done (1799 ms)
Verifying image signature...done (1 ms)
Firmware Valid.
Flattened uImage Tree: Version 17, Size 87561128
Decompressing Image fpga-1 (gzip): 0x151E31C0 -> 0x60000000 (1694771 bytes)
Decompressed fpga-1: 26510780 bytes
Image fpga-1: 0x60000000 (26510780 bytes)
FIT: programming FPGA 'fpga-1' (26510780 bytes, full)
FPGA status: 0xA0002FDE
FIT: FPGA programmed
Decompressing Image kernel-1 (gzip): 0x10000100 -> 0x200000 (13164230 bytes)
Decompressed kernel-1: 33182208 bytes
Image kernel-1: 0x200000 (33182208 bytes)
Image fdt-cortexa53-linux.dtb: 0x10C8E0DC (75545 bytes)
Loading DTS: 0x10C8E0DC -> 0x1000 (75545 bytes)
Loading Image ramdisk-1: 0x10CA08C8 -> 0x40000000 (72624159 bytes)
Image ramdisk-1: 0x40000000 (72624159 bytes)
Loaded ramdisk: 0x40000000 (72624159 bytes)
FDT: Set chosen (45720), linux,initrd-start=1073741824
FDT: Set chosen (45720), linux,initrd-end=1146365983
Invalid elf, falling back to raw binary
Booting at 00200000
do_boot: entry=0x00200000, EL=2
do_boot: dts=0x00001000
FDT: Version 17, Size 75545
FDT: Set chosen (45720), bootargs=earlycon console=ttyPS0,115200 init_fatal_sh=1
do_boot: flushing caches, disabling MMU
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]

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