Changes needed for Glymur ES release#611
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The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various power domains including System, SoC, CPU clusters, GPU, and various other subsystems for glymur. Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com> Link: https://patch.msgid.link/20260519-qcom_spel_driver_upstream-v1-3-75356d1b7f94@oss.qualcomm.com
… operation Add explicit data-lanes to the MDSS DP output endpoints to enable display port in 2 lanes configuration and disable the mode-switch property from the USB QMP PHY node. Signed-off-by: Saurabh Anand <saurabh.anand@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260521120058.2966709-1-saurabh.anand@oss.qualcomm.com/
The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware based power monitoring and limiting capabilities for various power domains including System, SoC, CPU clusters, GPU, and various other subsystems. The driver integrates with the Linux powercap framework, exposing SPEL capabilities through powercap sysfs interfaces. This allows userspace applications and thermal management daemons to monitor energy consumption and configure power limits for optimal power/performance balance. Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Test Matrix
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Test Matrix
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Below changes are needed for Glymur ES release :
QCLINUX: defconfig: Enable Qualcomm SPEL driver
FROMLIST: arm64: dts: qcom: glymur: Configure DP endpoints for 2-lane operation
FROMLIST: arm64: dts: qcom: glymur: Enable SPEL powercap driver