diff --git a/difftest b/difftest
index ca341b67..261b4413 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit ca341b6739b434562959184fc07ae42de4efbffd
+Subproject commit 261b4413184c901fa45bb3387f8c40a702d56ebd
diff --git a/src/main/scala/sim/NutShellSim.scala b/src/main/scala/sim/NutShellSim.scala
index ed6ec884..a6e8af0f 100644
--- a/src/main/scala/sim/NutShellSim.scala
+++ b/src/main/scala/sim/NutShellSim.scala
@@ -36,14 +36,17 @@ class NutShellSim extends Module with HasDiffTestInterfaces {
   soc.io.frontend <> mmio.io.dma
 
   memdelay.io.in <> soc.io.mem
+  mem.io.in <> memdelay.io.out
 
   mmio.io.rw <> soc.io.mmio
 
   soc.io.meip := mmio.io.meip
 
   override def cpuName: Option[String] = Some("NutShell")
-  val memIO = DifftestMemCtrl.exposeIO(memdelay.io.out, mem.io.in)
-  override def difftestMemIO: Option[DifftestMemIO] = Some(memIO)
+  val memIO = Option.when(DifftestModule.isFPGA) {
+    DifftestMemCtrl.exposeIO(memdelay.io.out, mem.io.in)
+  }
+  override def difftestMemIO: Option[DifftestMemIO] = memIO
 
   val uart = IO(new UARTIO)
   uart <> mmio.io.uart